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In this project, you will be completing the design of a simple general purpose processor using Xilinx ISE Schematic Capture.


In this project, you will be completing the design of a simple general purpose processor using Xilinx ISE Schematic Capture.

DISCLAIMER: The processor we are working with is a very basic 8 bit single cycle processor with no data memory. While it is a good representation of a general purpose processor and is good for education, commercial processors are typically more complex.

A skeleton has been provided that contains various aspects of the processor already designed. You will be completing the Arithmetic Logic Unit, Register File and Instruction Memory of the simple processor.

Below is a description of these units as it pertains to this processor. You will need to use these descriptions as well as the information in the architecture section to fully build these units.

Arithmetic Logic Unit (ALU):

As covered in class, the arithmetic unit does the arithmetic and logic lifting for the processor. This ALU is an 8 bit ALU and can do 8 different operations as described in the table below. You will build the components for these logic and arithmetic operations.




O = B


O = A ^ B (bitwise xor)


O = A AND B (bitwise and)


O = A OR  B (bitwise or)


O = A + B (addition)


O = A - B (subtract)


O(7) = 0, 0(6:0) = B (7:1) (logical shift right)


O = A * B (multiplication)

In addition to the operations, the ALU will also help generate flags based off the output. You do not have to create the flags but will need to create the input values for the carry flag multiplexor.

ALU inputs:

8 bit data to be operated on. This comes from  the register file, read data a(R_data_a).

B (7:0):

8 bit data to be operated on. This can come from the register file, read data b (R_data_b)  or the data input to the processor.

Opcode (2:0):
This picks the operation to be done. The opcode comes from instruction bits 6 down to 4.

ALU Outputs:

O (7:0):

The result of the ALU operation.


The carry flag, generated when we have over flow from the add, subtract or multiply operations


The sign flag, generated when we have negative result i.e if the most significant bit is a 1.


Zero flag, generated when we have a zero result.

Register File:

The register file for this processor contains our general purpose registers and is made of one write port, a bank of 4 registers (r0-r3) and two read ports. These will be used by the processor instructions to hold data as it is operated on.


Write Address (W_addr [1:0]):

The 2 bit address for the register to write data to after an instruction.

This address is also the same as the read address a (R_addr_a).

Write data (W_data[7:0]):

Data to be written to a register described by the write address.

Write Enable  (W_enable):

Enables saving the write data to the write register. This ensures that we only save data in a register during an instruction that actually needs to save data. For example an add instruction needs to save data but a jump instruction does not need to save any data

Read address a (R_addr_a[1:0]):
2 bit address of register to read data from. This is also write address.

Read address b (R_addr_b[1:0]):
Second 2 bit address of register to read data from.


Read data a (R_data_a [7:0]):
Data from register described by read address a.

Note: Depending on the instruction, the data in this register will get replaced as it also acts as the destination register.


Read data b (R_data_b [7:0]):

Data from register described by read address b.


Clock (>):
Clock input for the register file. This clock is tied to all the registers and should be the same clock for the entire processor.

Instruction Memory:

The instruction memory for this processor  is a read only memory (ROM) that gets initialized with data and can only be read from. In our case this initialization will happen as we design the rest of the processor in xilinx.

You will not be designing the instruction rom for the processor but you will be writing a program. The skeleton comes with a program preloaded described as below:

The program you will be writing is described in pseudo code below. You will need to convert it into our processor’s assembly language and then into machine code:


START:           MIN=127

LOOP:             If MIN==0, Goto END

                        Load X (X comes from the input to the processor)

                        P=|X| (absolute value of x)

                        If P < MIN, MIN=P 

                        Goto LOOP

END:               Goto END


How to enter instructions into the Instruction ROM:

Once you have your instructions broken down into assembly, you will need to change them to machine code (binary) as discussed in class.

In order to enter the binary into the instruction rom in Xilinx you will need to follow these steps:

  • Convert the binary to HEX.
  • Go to the Instruction Rom schematic. You can get there by either:
    • Double Clicking on the Instruction PROM schematic in the Design Window.
    • Pushing into the GPP symbol then the Instruction ROM symbol.
      • You push into a symbol by right clicking on it -> Symbol -> Push into symbol.
    • Note: In the Instruction ROM, the inputs to the MUX represent the instruction to be executed. The Select signal for the mux is the instruction address aka the instruction to be executed next. This is fed from the PC.
    • The instructions are in order so the instruction tied to input 0 of the mux would be your first instruction and input 1 would be your second and so on.
  • Once in the ROM double click on the constant box tied to the input of the instruction you need to edit.
  • Edit the CValue in the pop window with the HEX value of the instruction you need.
  • Save and synthesize the entire project. You do not need to synthesize just the Instruction ROM.



It is encouraged that you test your work as you go along. To aide in this, the skeleton comes with three separate test benches (simulation files) that you can use to test your designs.

ALU Test Bench

The ALU Test bench is labelled: ALU_ALU_sch_tb

This testbench steps through all the opcode values in order starting from 000 up to 111.

The values for A and B are currently both set to the binary value “10101010”.

To use the text bench:

  • Run the simulation as you would normally.
  • Check the output for the opcode you are currently testing against the output (O).
    • For example, if I have built the adder and I would like to test it, then I would put adder component output to input 4 (100)  of my  mux and run the test bench. I would then check the output value (0) when the opcode is 100. The output should be the result of adding 101010102 + 101010102.

You do not need to have all the components built in the ALU to test an individual one, but you do need to have the multiplexor component built at the very least before you can test the rest of the components.

Register File Test Bench

The register file testbench is labelled: RegFile_RegFile_sch_tb

This test bench tests whether or not the registers load when the write enable is high and whether the correct data is read from the correct register.


The testbench oscillates the write enable signal, while stepping through all the registers addresses for both read addresses as well as the write address.

The data to be input (wr_data), changes by an increment of 8 on each iteration.

When ready to test, run the simulation, and compare the address inputs with data outputs.

Although not set up by default in the waveform window, you can also add the registers themselves to the waveform.

To do this:

  • Run the reg file simulation
  • Once the waveform window opens, go to the window on the left hand side and click on the arrow right next to regfile_regfile_sch
  • Click on UUT
  • In the window between the one you are currently in and the waveform window, look for the names of your register symbols. Drag and drop these into the waveform
  • Hit the reset button at the top of the waveform window (blue refresh arrow button) then run the simulation again using the blue play button with an hourglass next to it. (Do not use the blue play button without the hour glass)
  • You should now be able to see the contents of the different registers as they change

Do not change anything in the source code for this simulation file

GPP Test Bench

This test bench tests the entire processor once the register file and ALU are done. It is named: GPPTestCircuit_GPPTestCircuit_sch_tb.

It is set up to test the default program that came with the skeleton, however it can be changed to test the  program you are supposed to write.

Instructions on how to make that change are in the test bench itself and you can get to it by double clicking on the name of the test bench.

For the default program, the inputs are set to 10 and 2. Thus it is testing 10/2 and the result should be stored in R0 when the program finishes.


For the program you write, the sequence of inputs in the testbench is as follows:

MIN =127

X= 10










You can change the inputs to what you want to test in the test bench by changing the binary value of Input in the sequence. 

Implementation Details & Hints:

  • You can work in groups of 1-2 students.
  • Review the Architecture Section.
  • You must use schematics. You CANNOT use VHDL or Verilog in your design.
  • You should design using components. Build and design the components one step at a time from the bottom up.
  • You cannot use any of the inbuilt adders, subtractors or other xilinx arithmetic built in components. Flip flops (FD/FDE), D- Latches(LD), Multiplexors and decoders are ok.
    • You CANNOT use the multi bit flip flops
    • You CANNOT use the Mux8_8, reg16 or reg2 components
    • Any multibit component needed has to be built by you
  • A skeleton has been provided. In addition to the empty ALU and Register File, the skeleton also contains simulation files for the ALU, Register File and the processor as a whole.
    • The ALU simulation file tests all possible operations on two inputs.
    • The Register file, tests loading values into all the registers and reading values from them.
    • The general simulation file, tests the first algorithm as described above. It also tests the second algorithm that you are required to build.
  • DO NOT change the inputs or outputs in the skeleton.
  • DO NOT change any of the schematics outside of the ones required for the project.
    • If you make any changes, redownload the skeleton and copy your work over as needed.
  • You will need to zip up the entire folder your project is located in and submit it on blackboard
    • If you worked alone you should label the zip file as: lastname_firstname_project3.zip
    • If you worked as a team label the zip file as: lastname_firstname_lastname_firstname_project3.zip
  • Any late submissions will incur a penalty of 10 points per every 6 hours they are late.

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